https://www.yo3iti.ro/index.php?action=history&feed=atom&title=Despre_Arty_Z7 2026-11-03T22:39:29Z Istoricul versiunilor pentru această pagină din wiki MediaWiki 1.45.1 https://www.yo3iti.ro/index.php?title=Despre_Arty_Z7&diff=3746&oldid=prev 2026-11-03T19:08:57Z

<p>Pagină nouă: ==Proprietățile FPGA din Arty Z7== Pentru Arty Z7, part name este: &lt;syntaxhighlight lang=&quot;tcl&quot;&gt; report_property [get_parts xc7z020clg400-1] &lt;/syntaxhighlight&gt; Cu proprietățile: &lt;syntaxhighlight lang=&quot;debug&quot;&gt; Property Type Read-only Value ARCHITECTURE string true zynq ARCHITECTURE_FULL_NAME string true Zynq-7000 AVAILABLE_CONFIG_MODES string* true {JTAG/Boundary Scan} AVAILABLE_IOBS int tr...</p> <p><b>Pagină nouă</b></p><div>==Proprietățile FPGA din Arty Z7==<br /> Pentru Arty Z7, part name este:<br /> &lt;syntaxhighlight lang=&quot;tcl&quot;&gt;<br /> report_property [get_parts xc7z020clg400-1]<br /> &lt;/syntaxhighlight&gt;<br /> Cu proprietățile:<br /> &lt;syntaxhighlight lang=&quot;debug&quot;&gt;<br /> Property Type Read-only Value<br /> ARCHITECTURE string true zynq<br /> ARCHITECTURE_FULL_NAME string true Zynq-7000<br /> AVAILABLE_CONFIG_MODES string* true {JTAG/Boundary Scan}<br /> AVAILABLE_IOBS int true 125<br /> BLOCK_RAMS int true 140<br /> CLASS string true part<br /> COLS int true 187<br /> COMPATIBLE_PARTS string* true xc7z010clg400<br /> C_FAMILY string true zynq<br /> DEVICE string true xc7z020<br /> DSP int true 220<br /> FAMILY string true zynq<br /> FE int true 0<br /> FLIPFLOPS int true 106400<br /> GB_TRANSCEIVERS int true 0<br /> IDCODE string true 0x03727093<br /> IO_PIN_COUNT int true 400<br /> IO_STANDARDS string true LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 HSUL_12 HSTL_I HSTL_II HSTL_I_18 HSTL_II_18 SSTL18_I SSTL18_II SSTL15 SSTL15_R SSTL135 SSTL135_R DIFF_HSTL_I DIFF_HSTL_II DIFF_HSTL_I_18 DIFF_HSTL_II_18 DIFF_SSTL18_I DIFF_SSTL18_II DIFF_SSTL15 DIFF_SSTL15_R DIFF_SSTL135 DIFF_SSTL135_R DIFF_HSUL_12 PCI33_3 MOBILE_DDR DIFF_MOBILE_DDR BLVDS_25 LVDS_25 RSDS_25 TMDS_33 MINI_LVDS_25 PPDS_25<br /> LUT_ELEMENTS int true 53200<br /> MAX_OPERATING_TEMPERATURE int true 0<br /> MAX_OPERATING_VOLTAGE double true 1.050<br /> MCBS int true 0<br /> MIN_OPERATING_TEMPERATURE int true 0<br /> MIN_OPERATING_VOLTAGE double true 0.950<br /> MMCM int true 4<br /> NAME string true xc7z020clg400-1<br /> PACKAGE string true clg400<br /> PACKAGE_PINOUT_VERSION string true FINAL 2012-06-26<br /> PACKAGE_PIN_DELAY_VERSION string true VERS. 2.0 2012-06-26<br /> PCI_BUSES int true 0<br /> REF_OPERATING_TEMPERATURE int true 0<br /> REF_OPERATING_VOLTAGE double true 0.950<br /> ROWS int true 157<br /> SLICES int true 13300<br /> SLRS int true 1<br /> SPEED string true -1<br /> SPEED_LABEL string true PRODUCTION<br /> SPEED_LEVEL_ID string true 1.12<br /> SPEED_LEVEL_ID_DATE string true 2019-11-22<br /> SSN_REPORT bool true 1<br /> SUPPORTS_NEXTGEN_VERSAL bool true 0<br /> TEMAC_NETWORK_CONTROLLERS int true 0<br /> TEMPERATURE_GRADE_LETTER string true <br /> &lt;/syntaxhighlight&gt;</div>

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