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Acesta a fost unul dintre testele date în cursul de FPGA de la Coursera: reproducerea în FPGA a unui numărător LS74163. Simularea în ModelSim:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
-- https://en.wikibooks.org/wiki/VHDL_for_FPGA_Design/4-Bit_Binary_Counter_with_Parallel_Load
entity AAC2M2P1 is port ( -- toate astea sunt din documentația LS74163
CP: in std_logic; -- clock
SR: in std_logic; -- Active low, synchronous reset
P: in std_logic_vector(3 downto 0); -- Parallel input = Data in
PE: in std_logic; -- Parallel Enable (Load)
CEP: in std_logic; -- Count enable parallel input, must be 1
CET: in std_logic; -- Count enable trickle input, must be 1
Q: out std_logic_vector(3 downto 0); -- Parallel output = Data out
TC: out std_logic -- Terminal Count/ RCO - ripple carry out
);
end AAC2M2P1;
architecture LS74163_A of AAC2M2P1 is
signal tmp_output : std_logic_vector(3 downto 0);
signal carry_on : std_logic;
begin
count_process : process (CP)
begin
if (CP'event and CP = '1') then
if (SR = '0') then
tmp_output <= (others => '0');
--carry_on <= '0';
else
if (PE = '0') then
tmp_output <= P;
--carry_on <= '0';
else
if (CEP = '1' and CET = '1') then
tmp_output <= tmp_output + 1;
if (tmp_output = "1111") then
carry_on <= '1';
else
carry_on <= '0';
end if;
end if;
end if;
end if;
end if;
end process count_process;
Q <= tmp_output;
TC <= carry_on;
end architecture LS74163_A;