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module logic_gates (
    input wire a,
    input wire b,
    output wire y0,
    output wire y1,
    output wire y2
);
assign y0 = ~a;
assign y1 = ~(a&b);
assign y2 = ~(a|b);
endmodule

Și un testbench:

`timescale 1ns/1ps

module logic_gates_tb;
    // Declare testbench signals
    reg a, b;
    wire y0, y1, y2;
    
    // Instantiate the design under test (DUT)
    logic_gates dut (
        .a(a),
        .b(b),
        .y0(y0),
        .y1(y1),
        .y2(y2)
    );
    
    // Test stimulus
    initial begin
        // Create VCD file for waveform viewing
        $dumpfile("logic_gates.vcd");
        $dumpvars(0, logic_gates_tb);
        
        // Display header
        $display("Time\t a b | y0(NOT) y1(NAND) y2(NOR)");
        $display("----------------------------------------");
        
        // Test all input combinations
        a = 0; b = 0; #10;
        $display("%0t\t %b %b |   %b       %b        %b", $time, a, b, y0, y1, y2);
        
        a = 0; b = 1; #10;
        $display("%0t\t %b %b |   %b       %b        %b", $time, a, b, y0, y1, y2);
        
        a = 1; b = 0; #10;
        $display("%0t\t %b %b |   %b       %b        %b", $time, a, b, y0, y1, y2);
        
        a = 1; b = 1; #10;
        $display("%0t\t %b %b |   %b       %b        %b", $time, a, b, y0, y1, y2);
        
        // End simulation
        #10;
        $display("\nSimulation completed successfully!");
        $finish;
    end
endmodule

Se compilează cu

#!/bin/bash

# Compile
iverilog -o sim logic_gates.v logic_gates_tb.v

# Run simulation
vvp sim

# Open waveform
surfer logic_gates.vcd

Rezultate:

(venv) tom@MacBook-Pro-Miron logic_gates % vvp sim
VCD info: dumpfile logic_gates.vcd opened for output.
Time     a b | y0(NOT) y1(NAND) y2(NOR)
----------------------------------------
10000    0 0 |   1       1        1
20000    0 1 |   1       1        0
30000    1 0 |   0       1        0
40000    1 1 |   0       0        0

Simulation completed successfully!
logic_gates_tb.v:43: $finish called at 50000 (1ps)

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