Divizor cu 16

/*
Un exemplu de divizor cu 16 care folosește metoda flip-flop-urilor în cascadă
*/

module clock_divider(
  input clk,
  input reset,
  output reg clk_div2,
  output reg clk_div4,
  output reg clk_div8,
  output reg clk_div16
);
  
  // Initialize on reset
  always @(posedge clk or posedge reset) begin
    if (reset)
      clk_div2 <= 1'b0;
    else
      clk_div2 <= ~clk_div2;
  end

  always @(posedge clk_div2 or posedge reset) begin
    if (reset)
      clk_div4 <= 1'b0;
    else
      clk_div4 <= ~clk_div4;
  end

  always @(posedge clk_div4 or posedge reset) begin
    if (reset)
      clk_div8 <= 1'b0;
    else
      clk_div8 <= ~clk_div8;
  end

  always @(posedge clk_div8 or posedge reset) begin
    if (reset)
      clk_div16 <= 1'b0;
    else
      clk_div16 <= ~clk_div16;
  end

endmodule

Divizor cu 16, verilog

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